1. Field of the Invention
The invention relates to a metallization process for integrated circuit devices, and more particularly, to a metallization process with improved electromigration and improved step coverage, especially for sub-micron feature sizes in the fabrication of integrated circuits.
2. Description of the Prior Art
For sub-micron feature sizes, metal step coverage and planarization processes are very difficult to implement. Typically, an insulating layer of borophosphosilicate glass (BPSG) 12 or the like is deposited over semiconductor device structures in and on a semiconductor substrate 10, as shown in FIG. 1. A contact opening is etched through the insulating layer 12 to the underlying substrate. A metal layer 14 is sputtered into the contact opening, as illustrated in FIG. 2. As the contact size decreases, the contact aspect ratio (contact height/ width) increases. The high aspect ratio inhibits the sputtered metal from going into the hole resulting in poor step coverage. Planarization is poor because the conducting layers tend to shrink more aggressively in the horizontal direction than in the vertical direction resultting in a more severe topography to planarize.
Methods such as hot aluminum plugs, O.sub.3 tetraethoxysilane (TEOS), and other planarization schemes have been used by workers in the art. It is desirable to solve the metal step coverage and planarization problems with the least effort.
U.S. Pat. No. 5,324,975 to Kumagai et al shows a typical contact and conductor line layout.